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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Depletion-load NMOS logic ： ウィキペディア英語版 Depletion-load NMOS logic In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier nMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements. Some depletion-load nMOS designs are still produced, typically in parallel with newer CMOS counterparts; one example of this is the Z84015〔''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015''.〕 and Z84C15.〔''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15''.〕 Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early pMOS and nMOS chips demanded several voltages). The inclusion of depletion-mode n-MOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation. ==History and background== 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Depletion-load NMOS logic」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.